3d chip stack having encapsulated chip-in-chip

ABSTRACT

A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

BACKGROUND

The application is a divisional of U.S. patent application Ser. No.12/689,455 filed Jan. 19, 2010, the entire content and disclosure whichare incorporated herein by reference.

Multi-story chip technology is in demand for use in small electronicdevices including cell phones, digital cameras, personal digitalassistant (PDA), global positioning systems (GPS), and laptop computers,etc. Multi-story chip technology structures are formed by one chip beingvertically bonded to another chip. Such multi-story chip assembly whichis also known as a 3D-chip stack, allows a plurality of flash memorychips or a CPU to be stacked with at least one memory chip and othertypes of chips. In some examples, the wires that have been typicallyused to connect stacked chips have been replaced with metal pins thatare formed by drilling through each die's silicon and filling the holeswith a metal. These in-silicon pins are called “through-silicon vias”(TSV).

SUMMARY

The present disclosure, in some embodiments, provides athree-dimensional (3D) chip integration scheme having a chip-in-chip(CIC) structure. In one embodiment, a structure is provided thatincludes a first chip including first electrical devices present thereinand having a recess present therein, and a second chip including secondelectrical devices present therein, in which the second chip ispositioned within the recess of the first chip. In one embodiment,interconnects are formed to at least one of the second electricaldevices of the second chip that extend through the first chip intocontact with the second chip.

In another aspect, a method of forming a three-dimensional (3D) chip isprovided. In one embodiment, the method includes forming a recess in afirst chip, and positioning a second chip within the recess of the firstchip. The first chip includes first electrical devices, and the secondchip includes second electrical devices. Interconnects may be formedthrough the first chip into electrical communication with at least oneof the second electrical devices on the second chip.

DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, wherein like referencenumerals denote like elements and parts, in which:

FIG. 1 is a side cross-sectional view depicting one embodiment offorming a first etch mask on a second protective layer of a first chip,in which the first chip includes a first protective layer, a first bodyand the second protective layer, in accordance with one embodiment ofthe present invention.

FIG. 2 is a side cross-sectional view of forming a recess in the firstchip through the second protective layer and into the first body, inwhich the first chip includes first electrical devices, in accordancewith one embodiment of the present invention.

FIG. 3 is a side cross-sectional view of positioning a second chipwithin the recess of the first chip, wherein the second chip includes asecond body and contact pads present in an interlevel dielectric layer,in accordance with one embodiment of the present invention.

FIG. 4 is a side cross-sectional view of forming a second etch mask onthe second protective layer of the first chip, in accordance with oneembodiment of the present invention.

FIG. 5 is a side cross-sectional view of etching the second dielectriclayer and the first body selective to the contact pads of the secondchip to provide a via, and forming a dielectric liner on the sidewallsof the via, in accordance with one embodiment of the present invention.

FIG. 6 is a side cross-sectional view of filling the via with aconductive material to provide interconnects through the first chip intoelectrical communication with at least one of the second electricaldevices on the second chip, in accordance with one embodiment of thepresent invention.

FIG. 7 is a side cross-sectional view of a multi-layered electronicdevice including two levels each including a second chip that is presentembedded within a first chip in a chip-in-chip integration structure, inaccordance with one embodiment of the present invention.

FIG. 8 is a side cross-sectional view of a multi-layered electronicdevice including two levels each including a second chip that is presentembedded within a first chip, and a third level that does not include anembedded chip, in accordance with one embodiment of the presentinvention.

DETAILED DESCRIPTION

Detailed embodiments of the present invention are disclosed herein;however, it is to be understood that the disclosed embodiments aremerely illustrative of the invention that may be embodied in variousforms. In addition, each of the examples given in connection with thevarious embodiments of the invention is intended to be illustrative, andnot restrictive. Further, the figures are not necessarily to scale, somefeatures may be exaggerated to show details of particular components.Therefore, specific structural and functional details disclosed hereinare not to be interpreted as limiting, but merely as a representativebasis for teaching one skilled in the art to variously employ thepresent invention.

The embodiments of the present invention relate to methods of formingthree-dimensional (3D) chips, in which a second chip, e.g., child chip,is present encapsulated within a first chip, e.g., mother chip, toprovide a chip-in-chip integration structure. Specifically, a recess isformed in the first chip having a geometry that is configured forhousing the second chip. In one embodiment, the exterior face of thesecond chip is substantially coplanar with a backside surface of thefirst chip to provide a substantially co-planar bonding surface. A viacontaining a conductive material, such as a through silicon via, isformed through the first chip reaching the second chip. In someembodiments, the planar bonding surface that is provided by thechip-in-chip integration structure produced by encapsulating the secondchip within the first chip facilitates the production of multi-layeredelectronic devices. When describing the inventive method and structures,the following terms have the following meanings, unless otherwiseindicated.

As used herein, “semiconductor device” refers to an intrinsicsemiconductor material that has been doped, that is, into which a dopingagent has been introduced, giving it different electrical propertiesthan the intrinsic semiconductor. Doping involves adding dopant atoms toan intrinsic semiconductor, which changes the electron and hole carrierconcentrations of the intrinsic semiconductor at thermal equilibrium. Adominant carrier concentration in an extrinsic semiconductor determinesthe conductivity type of the semiconductor.

“Electrical communication” as used through the present disclosure meansthat a first structure and a second structure are connected by amaterial having a room temperature conductivity of greater than10⁻⁸(Ω-m)⁻¹.

“Embedded” means that at least a first portion of a second chip ispresent within a first chip.

“Encapsulated” means that a second chip is embedded within a first chip,in which the second chip has at least one exterior face that is coplanarwith at least one exterior face of the first chip, or the second chip isembedded within the first chip so the entirety of the second chip iswithin the first chip.

The term “direct contact” means that a first element, such as a firststructure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

“Planarization” is a material removal process that employs at leastmechanical forces, such as frictional media, to produce a planarsurface.

“Chemical Mechanical Planarization” is a material removal process usingboth chemical reactions and mechanical forces to remove material andplanarize a surface.

As used herein, the term “selective” in reference to a material removalprocess denotes that the rate of material removal for a first materialis greater than the rate of removal for at least another material of thestructure to which the material removal process is being applied.

As used herein, an “anisotropic etch process” denotes a material removalprocess in which the etch rate in the direction normal to the surface tobe etched is greater than in the direction parallel to the surface to beetched.

The terms “overlying”, “atop”, “positioned on” or “positioned atop”means that a first element, such as a first structure, is present on asecond element, such as a second structure, wherein interveningelements, such as an interface structure, e.g. interface layer, may bepresent between the first element and the second element.

FIG. 1 depicts one embodiment of a first chip 10, e.g., a mother chip,that has been fabricated with device and circuits in accordance withfront end of the line (FEOL) manufacturing processes, and includesinterconnects that have been fabricating in accordance with back end ofthe line (BEOL) manufacturing processes. The first chip 10 typicallyincludes a first body 11, a first protective layer 12 present on a frontside of the first body 11, and a second protective layer 13 present on aback side of the first body 11. The first body 11 typically includesfirst electrical devices present therein, such as semiconductor devices.For example, the first electrical devices that are present in the firstbody 11 may include transistors such as field effect transistors, e.g.,MOSFETS and CMOS devices, and the first body 11 may include bipolarjunction transistors. In another embodiment, the first electricaldevices of the first body 11 may include memory devices, such as flashmemory, dynamic random access memory (DRAM), and embedded dynamic randomaccess memory. It is noted that the first electrical devices presentwithin the first body 11 may not be limited to the above notedelectrical devices, as the first body 11 may include any combination ofthe aforementioned devices, as well as any transistor, inductor,capacitors, resistors, fuse and/or diode used in memory or logicdevices.

Typically, the first body 11 includes at least one substrate of asemiconductor material, which may provide the active region of at leastone of the aforementioned devices that are present within the first body11. The substrate may include any number of active and/or passivedevices (or regions) located within the substrate or on a surfacethereof. For example, the substrate may comprise any semiconductormaterial including, but not limited to Si, Ge, SiGe, SiC, SiGeC, InAs,GaAs, InP and other III/V compound semiconductors. The substrate may beundoped, or doped. In one example, the doping of a Si-containingsubstrate may be light (having a dopant concentration of less than 1E17atoms/cm³) or heavy (having a dopant concentration of about 1E17atoms/cm³ or greater). The substrate can have any crystallographicorientation such as (100), (110) or (111). Hybrid substrates having atleast two planar surfaces of different crystallographic orientation arealso contemplated.

For illustrative purposes, in the embodiments in which the first body 11includes field effect transistors (FETs), one example of a processsequence employed during front end of the line (FEOL) processing toprovide field effect transistors includes the following: field oxidationof the semiconductor substrate; patterning of the field oxide to definean active region and depositing a gate dielectric on an exposed surfaceof the semiconductor substrate; forming a gate conductor on the gatedielectric, patterning the gate conductor and gate dielectric to providea gate structure; and ion implantation of the exposed portion of thesemiconductor substrate adjacent to the gate structure with n-type orp-type dopants to provide source and drain regions. It is noted thatabove sequence is not intended to limit the invention, as other processsteps may be employed during front end of the line (FEOL) processing.For example, multiple device regions may be independently process byutilizing photolithography processes. The multiple device regions may beisolated from each other by isolation regions produced by localoxidation of silicon or trench isolation formation.

For illustrative purposes, in the embodiments in which the first body 11includes field effect transistors (FETs), one example of a processsequence employed during back end of the line (BEOL) processing toprovide an interconnect structure to the field effect transistorsincludes the following: blanket depositing a layer of dielectricmaterial atop the semiconductor substrate; planarizing the blanket layerof dielectric material; patterning and etched the dielectric layer toform via holes to the various source regions and drain regions and gateconductor structures; forming conductive studs within the vias; andforming an interconnect line in electrical communication with theconductive studs. It is noted that above sequence is not intended tolimit the invention, as other process steps may be employed during backend of the line (BEOL) processing.

In one embodiment, the first body 11 is provided from a wafer that hasbeen sectioned. For example, the first body 11 may have been diced.Wafer dicing is a process by which individual silicon chips orintegrated circuits on a silicon wafer are separated following theprocessing of the wafer. The dicing process can be accomplished byscribing and breaking, by mechanical sawing, or by laser cutting. In oneembodiment, the thickness T₁ of the first body 11 ranges from 50 μm to150 μm. In another embodiment, the thickness T₁ of the first body 11ranges from 70 μm to 120 μm. In yet another embodiment, the thickness T₁of the first body 11 ranges from 80 μm to 100 μm.

The first protective layer 12 and the second protective layer 13 aretypically composed of a dielectric material. The first protective layer12 and the second protective layer 13 may be composed of a same ordifferent dielectric material. In one embodiment, the first and secondprotective layer 12, 13 may be composed of an oxide, nitride oroxynitride material. In one example, the first and second protectivelayer 12, 13 are composed of silicon oxide. In another example, thefirst and second protective layer 12, 13 are composed of siliconnitride. The thickness of the first and second protective layers 12, 13may range from 1 μm to 15 μm, typically ranging from 5 μm to 10 μm. Thefirst and second protective layer 12, 13 may be formed on the first body11 of the first chip 10 using a deposition method including, but notlimited to spinning from solution, spraying from solution, chemicalvapor deposition (CVD), plasma enhanced CVD (PECVD), sputter deposition,reactive sputter deposition, ion-beam deposition, and evaporation.

Referring to FIGS. 1 and 2, the first chip 10 may be patterned andetched to provide a recess 20 having dimensions that are suitable tohouse a second chip, so that the second chip may be embedded andencapsulated within the first chip 10. In one embodiment, the recess 20in the first chip 10 may be formed using deposition, photolithographyand etching. For example, and as illustrated in FIG. 1 a first etch mask14 (also referred to as a block mask) is formed having an opening 15that exposes the portion of the first chip 10 in which the second chipwill subsequently be embedded. This portion of the first chip 10 iswhere the recess 20 will be formed.

The first etch mask 14 may comprise conventional soft and/or hardmaskmaterials and can be formed using deposition, photolithography andetching. In one embodiment, the first etch mask 14 comprises aphotoresist. A first etch mask 14 composed of photoresist can beproduced by applying a photoresist layer to the second protective layer13, exposing the photoresist layer to a pattern of radiation, anddeveloping the pattern into the photoresist layer utilizing a resistdeveloper to form the opening 15.

Alternatively, the first etch mask 14 can be a hardmask material.Hardmask materials include dielectric systems that may be deposited bychemical vapor deposition (CVD) and related methods. Typically, thehardmask composition includes silicon oxides, silicon carbides, siliconnitrides, silicon carbonitrides, etc. Spin-on dielectrics may also beutilized as a hardmask material including, but not limited tosilsequioxanes, siloxanes, and boron phosphate silicate glass (BPSG). Afirst etch mask 14 comprising a hardmask material may be formed byblanket depositing a layer of hardmask material, providing a patternedphotoresist atop the layer of hardmask material, and etching the layerof hardmask material to provide the opening 15.

FIG. 2 depicts one embodiment of etching the backside of the first chip10 to provide the recess 20. In one example, a timed etch is utilized tocontrol the depth D1 of the recess 20 so that it is 10% shallower thanthe thickness of the second chip that will be housed within the recess20. In one embodiment, the etch process is a two stage selective etch.For example, a first etch chemistry may remove the exposed portion ofthe second protective layer 13 selective to the first etch mask 14 andthe first body 11 of the first chip 10. Once the portion of the firstbody 11 underlying the opening 15 in the first etch mask 14 is exposed,a second etch chemistry may etch the exposed portion of the first body11 selective to the first etch mask 14. In one embodiment, the firstetch mask 14 may be removed during the first etch stage. In thisexample, the remaining portion of the second protective layer 13functions as an etch mask as the recess 20 is being etched into thefirst body 11 of the first chip 10. In the embodiments in which thefirst etch mask 14 remains on the second protective layer 13 after therecess 20 has been formed in the first chip 10, the first etch mask 14may be removed using an etch process. When the first etch mask 14 iscomposed of a photoresist material, the first etch mask 14 may beremoved by oxygen ashing or stripping.

In one embodiment, the etch process that provides the recess 20 includesan anisotropic etch process. The anisotropic etch may includereactive-ion etching (RIE). Reactive Ion Etching (RIE) is a form ofplasma etching in which during etching, the surface to be etched isplaced on the RF powered electrode. Moreover, during RIE the surface tobe etched takes on a potential that accelerates the etching speciesextracted from plasma toward the surface, in which the chemical etchingreaction is taking place in the direction normal to the surface. Otherexamples of anisotropic etching that can be used at this point of thedisclosure include ion beam etching, plasma etching or laser ablation.

The dimensions of the recess 20 are selected so that the second chip maybe housed within the recess so that it is embedded within the first chip10, and in some embodiments provides a planar backside surface. In oneembodiment, the recess 20 has a depth D1 ranging from 25 μm to 75 μm asmeasured from the exterior surface of the second protective layer 13. Inanother embodiment, the recess 20 has a depth D1 ranging from 35 μm to45 μm as measured from the exterior surface of the second protectivelayer 13. The width W1 of the recess 20 typically ranges from 50 μm to20,000 μm . In one embodiment, the width W1 of the recess 20 ranges from500 μm to 10,000 μm. In another embodiment, the width W1 of the recess20 ranges from 2,000 μm to 5,000 μm.

FIG. 3 depicts positioning a second chip 30 within the recess 20 of thefirst chip 10. The second chip 30 includes a second body 31 and padcontacts 32 that are present in an interlevel dielectric layer 33. Inone embodiment, and prior to introducing the second chip 30 to therecess 20 of the first chip 10, a conformal dielectric layer 16 isformed on the sidewall and base surfaces of the recess 20. The term“conformal” denotes a layer having a thickness that does not deviatefrom greater than or less than 20% of an average value for the thicknessof the layer. In one embodiment, the conformal dielectric layer 16 maybe formed using deposition techniques, such as chemical vapor deposition(CVD), atomic layer CVD (ALCVD), pulsed CVD, plasma of photo assistedCVD, sputtering, and chemical solution deposition. In anotherembodiment, the conformal dielectric layer 16 is formed by thermalgrowing process, which may include oxidation, oxynitridation,nitridation, and/or plasma or radical treatment. Suitable examples ofoxides that can be employed for the conformal dielectric layer 16include, but are not limited to SiO₂, Al₂O₃, ZrO₂, HfO₂, Ta₂O₃, TiO₂,perovskite-type oxides and combinations and multi-layers thereof. In oneembodiment, the conformal dielectric layer 16 has a thickness rangingfrom 50 nm to 550 nm. In another embodiment, the conformal dielectriclayer 16 has a thickness ranging from 100 nm to 500 nm. In yet anotherembodiment, the conformal dielectric layer 16 has a thickness rangingfrom 150 nm to 450 nm.

FIG. 3 depicts one embodiment of a second chip 30, e.g., a child chip,that has been fabricated with devices and circuits in accordance withfront end of the line (FEOL) manufacturing processes, and includesinterconnect structures that have been fabricated in accordance withback end of the line (BEOL) manufacturing processes. The second chip 30typically includes a second body 31 including second electrical devicespresent therein, such as semiconductor devices. For example, the secondelectrical devices that are present in the second body 31 may includetransistors such as field effect transistors, e.g., MOSFETS and CMOSdevices, and the second body 31 may include bipolar junctiontransistors. In another embodiment, the second electrical devices of thesecond body 31 may include memory devices, such as flash memory, dynamicrandom access memory (DRAM), and embedded dynamic random access memory.It is noted that the second electrical devices present within the secondbody 31 may not be limited to the above noted electrical devices, as thesecond body 31 may include any combination of the aforementioneddevices, as well as any transistor, inductor, capacitors, resistors,fuse and/or diode used in memory or logic devices.

Typically, the second body 31 includes at least one substrate of asemiconductor material, which may provide the active region of at leastone of the aforementioned devices that are present within the secondbody 31. The substrate may include any number of active and/or passivedevices (or regions) located within the substrate, or on a surfacethereof. For example, the substrate may comprise any semiconductormaterial including, but not limited to Si, Ge, SiGe, SiC, SiGeC, InAs,GaAs, InP and other III/V compound semiconductors. The substrate may beundoped, or doped. In one example, the doping of a Si-containingsubstrate may be light (having a dopant concentration of less than 1E17atoms/cm³) or heavy (having a dopant concentration of about 1E17atoms/cm³ or greater). The substrate can have any crystallographicorientation such as (100), (110) or (111). Hybrid substrates having atleast two planar surfaces of different crystallographic orientation arealso contemplated. The second body 31 may further include dielectriclayers to provide electrical device passivation and interconnectstructures, such as studs and interconnect lines, to provide electricalcommunication to the second electrical devices present therein.

In one embodiment, an interlevel dielectric layer 33 having contact pads32 present therein is formed on at least one face of the second body 31of the second chip 30. The interlevel dielectric layer 32 may be blanketdeposited atop the entire surface of the second body 31 and planarized.The interlevel dielectric layer 33 may be selected from the groupconsisting of silicon-containing materials such as SiO₂, Si₃N₄,SiO_(x)N_(y), SiC, SiCO, SiCOH, and SiCH compounds, the aforementionedsilicon-containing materials with some or all of the Si replaced by Ge,carbon-doped oxides, inorganic oxides, inorganic polymers, hybridpolymers, organic polymers, such as polyamides or SiLK™, othercarbon-containing materials, organo-inorganic materials such as spin-onglasses and silsesquioxane-based materials, and diamond-like carbon(DLC, also known as amorphous hydrogenated carbon, α-C:H). Additionalchoices for the interlevel dielectric 32 include: any of theaforementioned materials in porous form, or in a form that changesduring processing to or from being porous and/or permeable to beingnon-porous and/or non-permeable.

The interlevel dielectric layer 33 may be formed by various methods wellknown to those skilled in the art, including, but not limited tospinning from solution, spraying from solution, chemical vapordeposition (CVD), plasma enhanced CVD (PECVD), sputter deposition,reactive sputter deposition, ion-beam deposition, and evaporation. Theinterlevel dielectric layer 33 typically has a thickness that rangesfrom 20 nm to 1000 nm. In another embodiment, the interlevel dielectriclayer 33 has a thickness that ranges from 100 nm to 300 nm.

In one embodiment, the interlevel dielectric layer 33 may be patternedand etched to form holes to the various interconnect structures to thesecond electrical devices present in the second body 31. In one example,the interlevel dielectric layer 33 may be patterned and etched usingdeposition, photolithography and deposition methods.

Following the formation of the openings within the interlevel dielectriclayer 33, contact pads 32 can be formed by depositing a conductive metalinto the openings using deposition methods, such as chemical vapordeposition, sputtering or plating. The conductive metal may include, butis not limited to tungsten, copper, aluminum, silver, gold, and alloysthereof. The contact pads 32 are typically in electrical communicationwith the series of interconnected structures, e.g., interconnect line,that provide electrical communication to the second electrical devicesthat are present in the second body 31.

Similar to the first chip 10, the second chip 30 may be provided from awafer that has been sectioned. In one embodiment, the second chip 30 hasbeen diced. The dicing process can be accomplished by scribing andbreaking, by mechanical sawing, e.g., or by laser cutting. In oneembodiment, the thickness T₂ of the second body 31 ranges from 20 μm to60 μm. In another embodiment, the thickness T₂ of the second body 31ranges from 30 μm to 50 μm. In yet another embodiment, the thickness T₂of the second body 31 ranges from 35 μm to 45 μm. The width W₂ of thesecond body 31 typically ranges from 50 μm to 20000 μm. In anotherembodiment, the width W₂ of the second body 31 ranges from 500 μm to5000 μm. It is noted that the above dimensions are provided forillustrative purposes only, as other dimensions have been contemplatedand are within the scope of the present disclosure, so long as thedimensions of the second body 31 are suitable for being housed in therecess 20 of the first chip 10.

Still referring to FIG. 3, in one embodiment, the second chip 30, e.g.,child chip, may be flip-chip bonded to the first chip 10, e.g., parentchip, in the recess 20 of the first chip 10. More specifically, theexposed surface of the contact pads 32 are brought into direct contactwith the conformal dielectric layer 16 that is present on at least thebase of the recess 20 in the first chip 10. The interconnect between thefirst chip 10 and the second chip 30 is provided by a flip-bond.Flip-bonding is a method for interconnecting semiconductor devices, suchas IC chips, to external circuitry with solder bumps that have beendeposited onto the chip pads, e.g., contact pads 32 of the second chip.In one embodiment, the solder bumps are composed of at least one of tin,lead, silver, copper and gold.

In one embodiment, flip-chip bonding between the first chip 10 and thesecond chip 30 is produced by thermal bonding. For example, duringthermal bonding the temperature ranges from 85° C. to 380° C. In anotherembodiment, the temperature ranges from 100° C. to 250° C. During theapplication of temperature and the optional application of pressure thesolder bumps experience reflow and create a bond between the contactpads 32 of the second chip 30 and the conformal dielectric layer 16 ofthe first chip 10.

In one embodiment, the backside surface of the second chip 30 iscoplanar with the remaining portion of the backside surface of the firstchip 10, which provides a planar surface for bonding to additional chiplayers. In some examples, a planarization process applied to thebackside surface of the second chip 30 is continued until contacting thesecond protective layer 13 that is present on the backside surface ofthe first chip 10. The planarization process may remove excess materialfrom the backside surface of the second chip 30 to ensure that thebackside surface of the second chip 30 is coplanar with the backsidesurface of the first chip 10. In one example, the planarization processis provided by chemical mechanical planarization (CMP). “ChemicalMechanical Planarization” is a material removal process using bothchemical reactions and mechanical forces to remove material andplanarize a surface.

FIGS. 4-6 depict one embodiment for forming electrical connections tothe first chip 10 and the second chip 30. In one embodiment, forming theelectrical connections includes forming interconnects 50 through thefirst chip 10 into electrical communication with the at least one of thesecond electrical devices on the second chip 30. In one example, formingthe interconnects 50 includes forming a second etch mask 61 on the firstprotective layer 12 of the first chip 10, and etching the exposedportions of the first protective layer 12, the first body 11, and theconformal dielectric layer 16 selective to the contact pads 31 of thesecond chip 30 to provide a via 40. A dielectric liner 41 may then beformed on the sidewalls of the via 40, wherein the via 40 and is filledwith a conductive material 42 to provide the interconnect 50. In oneexample, the interconnect 50 may be referred to as Through Semiconductor(e.g., silicon) Via (TSV).

FIG. 4 depicts one embodiment of forming a second etch mask 61 on thefirst protective layer 12 of the first chip 10. In one embodiment, thesecond etch mask 61 may comprise conventional soft and/or hardmaskmaterials and can be formed using deposition, photolithography andetching. In one embodiment, the second etch mask 61 comprises aphotoresist. In another embodiment, the second etch mask 61 can be ahardmask material. A second etch mask 61 composed of photoresist can beproduced by applying a photoresist layer to the first protective layer12, exposing the photoresist layer to a pattern of radiation, anddeveloping the pattern into the photoresist layer utilizing a resistdeveloper to form at least two opening. In one embodiment, the secondetch mask 61 includes a first opening 62 to provide via to at least onesecond electrical device that is present in the second chip, and asecond opening 63 to provide at least one via to at least one firstelectrical device or to another chip, i.e., mother chip.

In one embodiment, the second opening 63 of the second etch mask 61provides the pattern of a via that penetrates the entire thickness ofthe first chip 10, whereas the first opening 61 of the second etch mask61 provides the pattern of a via that penetrates only a portion of thethickness of the first chip 10. In one embodiment, the second opening 63of the second etch mask 61 has a greater width than the first opening 61of the second etch mask 61. In one embodiment, the first opening 62 hasa width d₃ ranging from 50 nm to 800,000 nm, and the second opening 63has a width d₄ ranging from 100 nm to 100,000 nm. In another embodiment,the first opening 62 has a width d₃ ranging from 1,000 nm to 10,000 nm,and the second opening 63 has a width d₄ ranging from 2,000 nm to 5,000nm.

FIG. 5 depicts etching the first protective layer 12 and the first body11 selective to the contact pads 32 of the second chip 30 to providevias 40, 45, and forming a dielectric liner 41 on the sidewalls of thevias 40, 45. In one embodiment, the vias 40, 45 are formed using an etchprocess, such as anisotropic etch process, e.g., reactive ion etch(RIE). In one example, the etch process is selective to the contact pads31 of the second chip 30. For example, the selective etch process may bea two stage etch. The first stage of the etch process may include anetch chemistry that removes the exposed portions of the first protectivelayer 12, selective to the first body 11, and the second etch mask 61.In a second stage of the etch process, the etch chemistry removes theexposed surface of the first body 11 selective to the second etch mask61 and the contact pads 32 of the second chip 30. In some embodiments,the second etch mask 61 may be removed by the etch chemistry of thefirst stage of the etching process. In this embodiment, the remainingportion of the first protective layer 12 provides the etch mask foretching the first body 11 selective to the contact pads 32.

The via 40 (hereafter referred to as contact pad via 40) that isprovided by the first opening 62 of the second etch mask 61 exposes thecontact pads 32 of the second chip 30. The via 45 (hereafter referred toas through first chip via 45) that is provided by the second opening 63of the second etch mask 61 may be utilized to contact the firstelectrical devices of the first chip 10 or may provide for electricalconnectivity to devices of an adjacent chip in a stacked chiparrangement.

FIG. 5 further depicts one embodiment of forming a dielectric liner 41on the sidewalls of the contact pad via 40 and the through first chipvia 45. The dielectric liner 41 may be composed of any dielectricmaterial including, but not limited to oxide, nitrides and oxynitrides.The dielectric liner 41 may be formed using conformal depositionmethods, such as plasma enhanced chemical vapor deposition, or thermalgrowth, such as thermal oxidation. In the embodiments in which thedielectric liner 41 is deposited by conformal deposition, the dielectricliner 41 that is deposited at the base of the via, such as the contactpads 32, is removed using an anisotropic etch process, such as reactiveion etch. The dielectric liner 41 typically has a thickness measuredfrom the sidewall of the via 40, 45 ranging from 1 nm to 20 nm, which insome embodiments may range from 5 nm to 10 nm.

FIG. 6 depicts filling the contact pad via 40 and the through first chipvia 45 with a conductive material 42 to provide interconnects 50 intothe first chip 10. In one embodiment, the contact pad via 40 is filledwith a conductive material 42, in which the conductive material is indirect physical contact with the contact pads 32, and provideselectrical communication to at least one of the second devices on thesecond chip 30. In one embodiment, the through first chip via 45 isfilled with a conductive material 42 to provide electrical communicationto an adjacent chip that is stacked on the first chip 10 having a secondchip 30 that is embedded therein. The through first chip via 45 may alsobe filled with a conductive material 42 to provide electricalcommunication to the first electrical devices that are present in thefirst chip 10. In one embodiment, the conductive material 42 is providedby a metal that may include, but is not limited to tungsten, copper,aluminum, silver, gold, and alloys thereof. The conductive material 42may be deposited within the vias 40, 45 using chemical vapor deposition(CVD), sputtering or plating. In some embodiments, following filling thevias 40, 45 with the conductive material 42, any of the conductivematerial 42 that extends to the exterior of the vias 40, 45 may beremoved using a planarization process, such as chemical mechanicalplanarization (CMP).

FIG. 6 also depicts forming interconnect contact pads 55 in directcontact with the interconnects 50. The interconnect contact pads 55typically have a width that is greater than the interconnects 50. In oneembodiment, forming the interconnect contact pads 55 includes etchingthe first protective layer 12 to provide an enlarged opening overlyingthe interconnect 50, filling the enlarged opening with a conductivematerial, and planarizing to remove any excess conducive material thatextends to the exterior of the enlarged opening. The interconnectcontact pads 55 may be composed of a metal that includes, but is notlimited to tungsten, copper, aluminum, silver, gold, and alloys thereof.The interconnect contact pads 55 may be formed using chemical vapordeposition (CVD), sputtering or plating.

The structure depicted in FIG. 6 is a chip-in-chip integration structure100 having a second chip 30, i.e., child chip, which is embedded and insome embodiments encapsulated within a first chip 10, i.e., parent chip.The chip-in-chip integration structure 100 includes a first chip 10including first electrical devices, in which the first chip 10 includesa recess present therein, a second chip 30 including second electricaldevices, in which the second chip 30 is positioned within the recess ofthe first chip 10; and interconnects 50 to at least one of the secondelectrical devices of the second chip 30 that are present through thefirst chip 10 into contact with the second chip 30.

FIG. 7 depicts one embodiment of stacking two chip-in-chip integrationstructures, in accordance with the present disclosure. Morespecifically, a first chip-in-chip integration structure 101 is presentoverlying a second chip-in-chip integration structure 102, in which afront face of the first chip-in-chip integration structure 101 is indirect contact with a front face of the second chip-in-chip integrationstructure 102. More specifically, the first protective layer 12 of thefirst chip-in-chip integration structure 101 is in direct contact withthe first protective layer 12 of the second chip-in-chip integrationstructure 102. It is observed that the first and second chip-in-chipintegration structures 101, 102 each are structurally similar to thechip-in-chip integration structure 100 that is depicted in FIG. 6. Inone embodiment, a first group of interconnects 50A is used to provideelectrical communication to the second chip 30 and a second group ofinterconnects 50B is used to provide electrical communication for chipstacking.

FIG. 8 depicts another example of chip stacking wherein the firstchip-in chip integration structure 101 and the second chip-in-chipintegration structure 102 that are depicted in FIG. 7 is further bondedto third chip 103. In one embodiment, the third chip 103 is a singlechip that does not include a second chip embedded therein. In oneexample, an extension 410, 420 that is present through the second chip30 of the second chip-in-chip 102 integration, and provides forelectrical communication between the interconnects 50A of the first andsecond chip-in-chip integration structures 101, 102 and theinterconnects 50B of the third chip integration structure 103.

While embodiments of the present invention have been described hereinfor purposes of illustration, many modifications and changes will becomeapparent to those skilled in the art. Accordingly, the appended claimsare intended to encompass all such modifications and changes as fallwithin the true spirit and scope of this invention.

What is claimed is:
 1. A layered electrical device comprising: a firstchip including first electrical devices, in which the first chipincludes a recess present therein; a second chip including secondelectrical devices, in which the second chip is positioned within therecess of the first chip; and interconnects to at least one of thesecond electrical devices of the second chip that are present throughthe first chip into contact with the second chip.
 2. The layeredelectrical device of claim 1, wherein the first electrical devicesinclude at least one device selected from the group consisting ofsemiconductors devices, memory devices, resistors, capacitors andcombinations thereof.
 3. The layered electrical device of claim 2,wherein the semiconductor devices are field effect transistors.
 4. Thelayered electrical device of claim 1, wherein the second electricaldevices include at least one device selected from the group consistingof semiconductors devices, memory devices, resistors, capacitors andcombinations thereof.
 5. The layered electrical device of claim 4,wherein the semiconductor devices are field effect transistors.
 6. Thelayered electrical device of claim 5, wherein the memory devices areselected from the group consisting of flash memory, dynamic randomaccess memory (DRAM), embedded dynamic random access memory andcombinations thereof.
 7. The layered electrical device of claim 1,wherein the second chip is encapsulated in the first chip.
 8. Thelayered electrical device of claim 7, wherein a conformal dielectriclayer is present on a base and sidewalls of the recess separating thesecond chip from the first chip.
 9. The layered electrical device ofclaim 8, wherein the second ship includes contacts present in contactwith the conformal dielectric layer that is present on the base andsidewalls of the recess.
 10. The layered electrical device of claim 9,wherein the interconnects extend through the first chip, and theconformal dielectric layer that is present on the base and sidewalls ofthe recess, wherein the interconnects are in direct contact with thecontacts of the second chip.
 11. The layered electrical device of claim1, wherein at least one of the first chip and the second chip includes asemiconductor material selected from the group consisting of Si, Ge,SiGe, SiC, SiGeC, InAs, GaAs, InP, III/V compound semiconductors andcombinations thereof.
 12. The layered electrical device of claim 1,wherein the first chip has a thickness ranging from 50 μm to 150 μm. 13.The layered electrical device of claim 1, wherein the recess in thesecond chip has a depth ranging from 25 μm to 75 μm, and a width rangingfrom 50 μm to 20,000 μm.
 14. The layered electrical device of claim 1,wherein the recess in the second chip has a depth ranging from 35 μm to45 μm, and a width ranging from 2,000 μm to 5,000 μm.
 15. The layeredelectrical device of claim 8, wherein the conformal dielectric layer iscomposed of a dielectric that is selected from the group consisting ofSiO₂, Al₂O₃, ZrO₂, HfO₂, Ta₂O₃, TiO₂, perovskite-type oxides andcombinations thereof.
 16. The layered electrical device of claim 8,wherein the conformal dielectric layer has a thickness ranging from 50nm to 550 nm.
 17. The layered electrical device of claim 8, wherein theconformal dielectric layer has a thickness ranging from 100 nm to 500nm.
 18. The layered electrical device of claim 1, wherein theinterconnects are of a metal selected from the group consisting oftungsten, copper, aluminum, silver, gold, and alloys thereof.